Interrupts: Difference between revisions

From Helpful
Jump to navigation Jump to search
mNo edit summary
mNo edit summary
Line 4: Line 4:
<!--
<!--


An interrupt (sometimes hardware trap) is a request by hardware for the processor to pause what it's doing and jump to whatever piece of code is registered for that specific interrupt -- you have a number of interrupts, classically each a dedicated hardware line, and pin on the CPU (though they are often shared by multiple devices, we try not to minimise that means additional bookkeeping to tell which actual device was the source).
In computers, an '''interrupt''' (sometimes hardware trap) is a request by hardware for the processor to pause what it's doing and jump to whatever piece of code is registered for that specific interrupt -- you have a number of interrupts, classically each a dedicated hardware line, and pin on the CPU (though they are often shared by multiple devices, we try not to minimise that means additional bookkeeping to tell which actual device was the source).




Most interrupts are used in a "hardware really can't wait for the CPU to get to it" way, which are very temporary, and not faults.
Most interrupts are used in a "I, this hardware, really require attention very soon, and don't want to wait for the CPU to think about us existing and [[polling]] us" way, which are very temporary, and not faults.


Interrupts ''can'' also be used to signal problems that we probably ''should'' consider fatal errors, particularly if there is value to do so sooner rather than later.
Interrupts ''can'' also be used to signal problems that we probably ''should'' consider fatal errors, particularly if there is value to do so sooner rather than later.




Line 44: Line 45:


https://en.wikipedia.org/wiki/Message_Signaled_Interrupts
https://en.wikipedia.org/wiki/Message_Signaled_Interrupts
[https://www.quora.com/How-does-a-hardware-interrupt-work-Does-it-use-its-own-bus-or-the-systems-bus-Is-it-the-same-for-software-interrupts This answer] has an interesting example with
: an 8086 (which has a single non-maskable interrupt pin shred for everything),
: plus a Programmable Interrupt Controller (8259)
:: that basically has the job of holding that 8086's NMI pin high as long as something is bothering the PIC
:: the 8086 will still have to know how to talk to the PIC





Revision as of 12:10, 17 October 2023

This article/section is a stub — some half-sorted notes, not necessarily checked, not necessarily correct. Feel free to ignore, or tell me about it.