Some understanding of memory hardware: Difference between revisions
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'''DRAM''' - Dynamic RAM | '''DRAM''' - Dynamic RAM | ||
: lower component count per cell than most (transistor+capacitor mainly), so high-density and cheaper | : lower component count per cell than most (transistor+capacitor mainly), so high-density and cheaper per storage size | ||
: yet capacitor leakage means this has to be refreshed regularly, meaning a DRAM controller, more complexity and higher latency than some | : yet capacitor leakage means it forgets its state, so this has to be refreshed regularly, | ||
: (... | : also meaning you need a DRAM controller, more complexity (not something you'd DIY), and higher latency than some | ||
: (...some latency is less of an issue when you have multiple chips) | |||
: this or a variant is typical as main RAM, due to low cost per bit | : this or a variant is typical as main RAM, due to low cost per bit | ||
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: ...that of coordinating the DRAM via an external clock signal (previous DRAM was asynchronous, manipulating state as soon as lines changed) | : ...that of coordinating the DRAM via an external clock signal (previous DRAM was asynchronous, manipulating state as soon as lines changed) | ||
: This allows the interface to that RAM to be a predictable state machine, which allows easier buffering, and easier interleaving of internal banks | : This allows the interface to that RAM to be a predictable state machine, which allows easier buffering, and easier interleaving of internal banks | ||
: | : which makes higher data rates a bunch simpler (though not necessarily lower latency) | ||
: SDR/DDR: | : SDR/DDR: | ||
:: DDR doubled busrate by widening the (minimum) units they read/write (double that of SDR), which they can do from single DRAM bank{{verify}} | :: DDR doubled busrate by widening the (minimum) units they read/write (double that of SDR), which they can do from single DRAM bank{{verify}} | ||
:: similarly, DDR2 is 4x larger units than SDR and DDR3 is 8x larger units than SDR | :: similarly, DDR2 is 4x larger units than SDR and DDR3 is 8x larger units than SDR | ||
:: DDR4 uses the same width as DDR3, instead doubling the | :: DDR4 uses the same width as DDR3, instead doubling the bus rate by interleaving from banks | ||
:: unrelated to latency, it's just that the bus frequency also increased over time. | :: unrelated to latency, it's just that the bus frequency also increased over time. | ||
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'''Graphics RAM''' | '''Graphics RAM''' is less of a type and more of a design specialization | ||
: Earlier versions would e.g. allow reads and writes (almost) in parallel, making for lower-latency framebuffers | : Earlier versions would e.g. allow reads and writes (almost) in parallel, making for lower-latency framebuffers | ||
: "GDDR" is a somewhat specialized form of DDR SDRAM | : "GDDR" is a somewhat specialized form of DDR SDRAM | ||
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: Retains state as long as power is applied to the chip, no need for refresh, also making it a little lower-latency | : Retains state as long as power is applied to the chip, no need for refresh, also making it a little lower-latency | ||
: no external controller, so simpler to use | : no external controller, so simpler to use | ||
: the higher component count per cell makes it more expensive per storage size | |||
: e.g used in caches, due to speed, and acceptable cost for lower amounts | : e.g used in caches, due to speed, and acceptable cost for lower amounts | ||
'''PSRAM''' - PseudoStatic RAM | '''PSRAM''' - PseudoStatic RAM | ||
: A tradeoff somewhere between SRAM and DRAM | : A design tradeoff, somewhere between SRAM and DRAM | ||
: | :: its like DRAM with built-in refresh, so functionally it's as "don't think about it" as SRAM | ||
: (yes, DRAM can have built-in refresh, but that's often points a ''sleep'' mode that retains state without requiring an active DRAM controller) | ::: (yes, DRAM technically can have built-in refresh, but that's often points a ''sleep'' mode that retains state without requiring an active DRAM controller, not something for active use) | ||
:: it's slower than DRAM, and cheaper than SRAM | |||
: SRAM makes sense for internal RAM, PSRAM makes sense for extended RAM in situations DRAM is not necessary | |||
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'''Non-volatile RAM''' | '''Non-volatile RAM''' | ||
While the concept of Random Access Memory (RAM) '''only''' tells you that you can access any part of it with comparable ease (contasted with e.g. tape storage, where more distance meant more time, so more storage meant more time)... | |||
...we tend to think about RAM as volatile, only useful as an intermediate scratchpad between storage and use, and will lose its contents as soon as it is unpowered. Probably because the commonly chosen designs have that property. | |||
Yet there are various designs that are both easily accessible ''and'' keep their state. | |||
And there is a gliding scale of ''various'' properties in that area as well. | |||
We may well call it NVM (non-volatile memory) when we haven't yet gotten to some more specific properties, like how often we may read or write, or how difficult that is. | We may well call it NVM (non-volatile memory) when we haven't yet gotten to some more specific properties, | ||
like how often we may read or write, or how difficult that is. | |||
Say, some variants of EEPROM aren't the easiest to deal with. We like Flash | Say, some variants of EEPROM aren't the easiest to deal with. | ||
We like Flash more, even though it's basically a development from EEPROM. | |||
But both wear out. | |||
NVRAM on the other hand tends to be easier, more reisable, like FRAM, MRAM, and PRAM, or nvSRAM or even BBSRAM. | NVRAM on the other hand tends to be easier, more reisable, like FRAM, MRAM, and PRAM, or nvSRAM or even BBSRAM. | ||
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'''nvSRAM''' - SRAM and EEPROM stuck on the same chip. | '''nvSRAM''' - SRAM and EEPROM stuck on the same chip. | ||
: seems intended as a practical improvement on BBSRAM | : seems intended as a practical improvement on BBSRAM | ||
: and/or a "access quickly, occasionally write a chunk to EEPROM" style of data logging, black boxes, that sort of thing | : and/or a "access common stuff quickly, occasionally write a chunk to EEPROM" style of data logging, black boxes, that sort of thing | ||
: https://en.wikipedia.org/wiki/NvSRAM | : https://en.wikipedia.org/wiki/NvSRAM | ||
'''BBSRAM''' - Battery Backed SRAM | '''BBSRAM''' - Battery Backed SRAM | ||
: basically just SRAM ''alongside'' a lithium battery, so that it'll live a good while | : basically just SRAM ''alongside'' a lithium battery, so that it'll live a good while | ||
: | : is sort of cheating, but usefully so. | ||
'''FRAM''' - Ferroelectric RAM | '''FRAM''' - Ferroelectric RAM | ||
: functions more like flash, also limited | : functions more like flash, also limited in amount of use (but with many more cycles) | ||
: read process is destructive (like e.g DRAM), so you need a write-after-read to keep data around | : read process is destructive (like e.g DRAM), so you need a write-after-read to keep data around | ||
: so it's great for things like | : so it's great for things like round-robin logging (which would be pretty bad for Flash) | ||
: https://electronics.stackexchange.com/questions/58297/whats-the-catch-with-fram | : https://electronics.stackexchange.com/questions/58297/whats-the-catch-with-fram | ||
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'''PRAM''' | '''PRAM''' | ||
: https://en.wikipedia.org/wiki/Phase-change_memory | : https://en.wikipedia.org/wiki/Phase-change_memory | ||
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'''ECC RAM''' | '''ECC RAM''' ('Error correction code') | ||
: can detect many (and correct some) hardware errors in RAM | : can detect many (and correct some) hardware errors in RAM | ||
: The rate of of bit-flips is low, but will happen. If your computations or data are very important to you, you want ECC. | : The rate of of bit-flips is low, but will happen. If your computations or data are very important to you, you want ECC rather than the regular, non-ECC type. | ||
: See also: | : See also: | ||
:: http://en.wikipedia.org/wiki/ECC_memory | :: http://en.wikipedia.org/wiki/ECC_memory | ||
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On pin count | On pin count | ||
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: ECC RAM has the same pin count | : ECC RAM has the same pin count | ||
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In any case, the type of memory must be supported by the memory controller | In any case, the type of memory must be supported by the memory controller | ||
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The name came from marketing, helping to distinguish it as its own thing with its own properties. | The name came from marketing, helping to distinguish it as its own thing with its own properties. | ||
Like EEPROM, Flash is non-volatile, has a limited number of erase cycles, and isn't the ''fastest'' to erase -- | |||
...yet arguably, "Flash memory" just means EEPROM that has block-level (or device-level) erase, | |||
making them faster to bulk-erase (so easier and faster to write) than the erase-bytes kind, | |||
a tradeoff that helps speed, cost, and use for random-storage needs. | a tradeoff that helps speed, cost, and use for random-storage needs. | ||
Simpler memory cards, and simpler USB sticks, have one flash chip and a simple controller, which is the cheapest setup and why they don't tend to break 10MB/s, | Simpler memory cards, and simpler USB sticks, have one flash chip and a simple controller, | ||
which is the cheapest setup and why they don't tend to break 10MB/s, | |||
and don't have enough wear leveling to last very long. | and don't have enough wear leveling to last very long. | ||
SSDs | SSDs are ''made of flash'', but | ||
* are what you might call managed flash. | |||
- | * go faster partly because they interleave/parallelize to multiple chips ([[RAID]]-like layout), | ||
: this also actually hides Flash's relatively slow erase speed (by doing it at other times, not when it's needed, a plan that usually works but may not under heavy load) and certain edge cases | |||
There are two types of Flash, NOR and NAND, named for the cells resembling (and working like) classical logic gates. | There are two types of Flash, NOR and NAND, named for the cells resembling (and working like) classical logic gates. | ||
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Very roughly, | Very roughly, | ||
NOR is faster but more expensive so has a few specialist uses, | NOR is faster but more expensive so has a few specialist uses, | ||
NAND is denser, slower, and takes less power, is typically more useful and cheaper for bulk storage. | NAND is denser, slower, and takes less power, is typically more useful and cheaper for bulk storage. | ||
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In other words, if you want a fresh copy of your data, read it all off, and write it back. | In other words, if you want a fresh copy of your data, read it all off, and write it back. | ||
{{comment|(...just as you should be doing on platter disks, and are also not doing)}}. | {{comment|(...just as you should be doing on platter disks, and are also not doing)}}. | ||
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==Flash, eMMC, UFS== | |||
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as mentioned, Flash is essentially a development upon EEPROM | |||
'managed flash' is one name you could give | |||
to putting a controller in front that does some amount of extra work. | |||
How complex that is varies, though. | |||
Worth mentioning is eMMC, basically a flash chip meant for internal use, that happens to be built on MMC. It was in common use for internal storage in phones and tables until it was displaced by UFS. | |||
"Are SD cards, USB flash drives managed flash?" | |||
(eUSB is Embedded, USB-connected flash. It's not un | |||
*Capacity Dependent | |||
In principle, eMMC and UFS are both managed (NAND) Flash, | |||
eMMC communication was scaled up from its origins. | |||
UFS communication is more modern, modeled off SCSI, | |||
For microcontrollers, both eMMC and UFS are nontrivial to interface | |||
if there isn't an existing interface, and you may prefer (micro)SD for now | |||
(most of which still support SPI, which was dropped from eMMC, despite shared origins), | |||
or use a platform that ''already'' interfaces with on-board whatever-it-is (probably eMMC, e.g. beagleboard). | |||
https://community.silabs.com/s/article/emmc-and-why-it-is-not-a-suitable-microcontroller-storage-option?language=en_US | |||
https://en.wikipedia.org/wiki/Universal_Flash_Storage | |||
UFS is mostly known in its embedded form (eUFS) | |||
: there are also UFS memory cards, but they are not (yet?) common | |||
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Revision as of 23:37, 30 March 2024
The lower-level parts of computers
General: Computer power consumption · Computer noises Memory: Some understanding of memory hardware · CPU cache · Flash memory · Virtual memory · Memory mapped IO and files · RAM disk · Memory limits on 32-bit and 64-bit machines Related: Network wiring notes - Power over Ethernet · 19" rack sizes Unsorted: GPU, GPGPU, OpenCL, CUDA notes · Computer booting
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"What Every Programmer Should Know About Memory" is a good overview of memory architectures, RAM types, reasons bandwidth and access speeds vary.
RAM types
DRAM - Dynamic RAM
- lower component count per cell than most (transistor+capacitor mainly), so high-density and cheaper per storage size
- yet capacitor leakage means it forgets its state, so this has to be refreshed regularly,
- also meaning you need a DRAM controller, more complexity (not something you'd DIY), and higher latency than some
- (...some latency is less of an issue when you have multiple chips)
- this or a variant is typical as main RAM, due to low cost per bit
SDRAM - Synchronous DRAM - is mostly a practical design consideration
- ...that of coordinating the DRAM via an external clock signal (previous DRAM was asynchronous, manipulating state as soon as lines changed)
- This allows the interface to that RAM to be a predictable state machine, which allows easier buffering, and easier interleaving of internal banks
- which makes higher data rates a bunch simpler (though not necessarily lower latency)
- SDR/DDR:
- DDR doubled busrate by widening the (minimum) units they read/write (double that of SDR), which they can do from single DRAM bank(verify)
- similarly, DDR2 is 4x larger units than SDR and DDR3 is 8x larger units than SDR
- DDR4 uses the same width as DDR3, instead doubling the bus rate by interleaving from banks
- unrelated to latency, it's just that the bus frequency also increased over time.
SRAM - Static RAM
- Has a higher component count per cell (6 transistors) than e.g. DRAM
- Retains state as long as power is applied to the chip, no need for refresh, also making it a little lower-latency
- no external controller, so simpler to use
- the higher component count per cell makes it more expensive per storage size
- e.g used in caches, due to speed, and acceptable cost for lower amounts
PSRAM - PseudoStatic RAM
- A design tradeoff, somewhere between SRAM and DRAM
- its like DRAM with built-in refresh, so functionally it's as "don't think about it" as SRAM
- (yes, DRAM technically can have built-in refresh, but that's often points a sleep mode that retains state without requiring an active DRAM controller, not something for active use)
- it's slower than DRAM, and cheaper than SRAM
- its like DRAM with built-in refresh, so functionally it's as "don't think about it" as SRAM
- SRAM makes sense for internal RAM, PSRAM makes sense for extended RAM in situations DRAM is not necessary
Non-volatile RAM
While the concept of Random Access Memory (RAM) only tells you that you can access any part of it with comparable ease (contasted with e.g. tape storage, where more distance meant more time, so more storage meant more time)...
...we tend to think about RAM as volatile, only useful as an intermediate scratchpad between storage and use, and will lose its contents as soon as it is unpowered. Probably because the commonly chosen designs have that property.
Yet there are various designs that are both easily accessible and keep their state.
And there is a gliding scale of various properties in that area as well.
We may well call it NVM (non-volatile memory) when we haven't yet gotten to some more specific properties,
like how often we may read or write, or how difficult that is.
Say, some variants of EEPROM aren't the easiest to deal with. We like Flash more, even though it's basically a development from EEPROM. But both wear out.
NVRAM on the other hand tends to be easier, more reisable, like FRAM, MRAM, and PRAM, or nvSRAM or even BBSRAM.
nvSRAM - SRAM and EEPROM stuck on the same chip.
- seems intended as a practical improvement on BBSRAM
- and/or a "access common stuff quickly, occasionally write a chunk to EEPROM" style of data logging, black boxes, that sort of thing
- https://en.wikipedia.org/wiki/NvSRAM
BBSRAM - Battery Backed SRAM
- basically just SRAM alongside a lithium battery, so that it'll live a good while
- is sort of cheating, but usefully so.
FRAM - Ferroelectric RAM
- functions more like flash, also limited in amount of use (but with many more cycles)
- read process is destructive (like e.g DRAM), so you need a write-after-read to keep data around
- so it's great for things like round-robin logging (which would be pretty bad for Flash)
- https://electronics.stackexchange.com/questions/58297/whats-the-catch-with-fram
PRAM
DRAM stick types
ECC RAM ('Error correction code')
- can detect many (and correct some) hardware errors in RAM
- The rate of of bit-flips is low, but will happen. If your computations or data are very important to you, you want ECC rather than the regular, non-ECC type.
- See also:
Registered RAM (sometimes buffered RAM) basically places a buffer on the DRAM modules (register as in hardware register)
- offloads some electrical load from the main controller onto these buffers, making it easier to have designs more stably connect more individual memory sticks/chips.
- ...at a small latency hit
- typical in servers, because they can accept more sticks
- Must be supported by the memory controller, which means it is a motherboard design choice to go for registered RAM or not
- pricier (more electronics, fewer units sold)
- because of this correlation with server use, most registered RAM is specifically registered ECC RAM
- yet there is also unregistered ECC, and registered non-ECC, which can be good options on specific designs of simpler servers and beefy workstations.
- sometimes called RDIMM -- in the same context UDIMM is used to refer to unbuffered
- https://en.wikipedia.org/wiki/Registered_memory
FB-DIMM, Fully Buffered DIMM
- same intent as registered RAM - more stable sticks on one controller
- the buffer is now between stick and controller [1] rather than on the stick
- physically different pinout/notching
SO-DIMM (Small Outline DIMM)
- Physically more compact. Used in laptops, some networking hardware, some Mini-ITX
EPP and XMP (Enhanced Performance Profile, Extreme Memory Profiles)
- basically, one-click overclocking for RAM, by storing overclocked timing profiles
- so you can configure faster timings (and Vdimm and such) according to the modules, rather than your trial and error
- normally, memory timing is configured according to a table in the SPD, which are JEDEC-approved ratings and typically conservative.
- EPP and XMP basically means running them as fast as they could go (and typically higher voltage)
In any case, the type of memory must be supported by the memory controller
- DDR2/3/4 - physically won't fit
- Note that while some controllers (e.g. those in CPUs) support two generations, a motherboard will typically have just one type of memory socket
- registered or not
- ECC or not
Historically, RAM controllers were a thing on the motherboard near the CPU, while there are now various cases where the controller is on the CPU.
More on...
DRAM versus SRAM
ECC
Buffered/registered RAM
EPROM, EEPROM, and variants
PROM is Programmable ROM
- can be written exactly once
EPROM is Erasable Programmable ROM.
- often implies UV-EEPROM, erased with UV shone through a quartz window.
EEPROM's extra E means Electrically Erasable
- meaning it's now a command.
- early EEPROM read, wrote, and erased (verify) a single byte at a time. Modern EEPROM can work in larger chunks.
- you only get a limited amount of erases (much like Flash. Flash is arguably just an evolution of EEPROM)