Some understanding of memory hardware: Difference between revisions

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(Created page with "{{computer hardware}} [https://people.freebsd.org/~lstewart/articles/cpumemory.pdf "What Every Programmer Should Know About Memory"] is a good overview of memory architectures, RAM types, reasons bandwidth and access speeds vary. ==RAM types== '''DRAM''' - Dynamic RAM : lower component count per cell than most (transistor+capacitor mainly), so high-density and cheaper : yet capacitor leakage means this has to be refreshed regularly, meaning a DRAM controller, more...")
 
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==RAM types==
==RAM types==
{{stub}}


'''DRAM''' - Dynamic RAM  
'''DRAM''' - Dynamic RAM  
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'''Graphics RAM''' refers to varied specialized
'''Graphics RAM''' refers to varied specialized
: Earlier versions would e.g. allow reads and writes (almost) in parallel, making for lower-latency framebuffers
: Earlier versions would e.g. allow reads and writes (almost) in parallel, making for lower-latency framebuffers
: "GDDR" is a somwhat specialized form of DDR SDRAM
: "GDDR" is a somewhat specialized form of DDR SDRAM




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'''Non-volatile RAM'''
'''Non-volatile RAM'''


The concept of Random Access Memory (RAM) '''only''' tells you that you can access any part of it with similar ease (contasted with e.g. tape storage, where more distance meant more time, so more storage meant more time).


Yet we tend to think about RAM as volatile, as entirely temporary scratchpad, only useful as an intermediate between storage and use.
While concept of Random Access Memory (RAM) '''only''' tells you that you can access any part of it with comparable ease (contasted with e.g. tape storage, where more distance meant more time, so more storage meant more time), we tend to think about RAM as volatile, only useful as an intermediate scratchpad between storage and use, and will lose its contents as soon as it is unpowered
 
This is perhaps because the simplest designs (and thereby cheapest per byte) have that property.  
This is perhaps because the simplest designs (and thereby cheapest per byte) have that property.  
For example, DRAM loses its charge and has to be constantly and actively refreshed, DRAM and SRAM and many others lose their state once you remove power.  
For example, DRAM loses its charge and has to be constantly and actively refreshed, DRAM and SRAM and many others lose their state once you remove power.
(There are also exceptions and inbetweeens, like DRAM that doesn't need its own controller and can be told to refresh itself in a low-power mode, acting a whole lot like SRAM).
 
(There are also exceptions and inbetweens, like DRAM that doesn't need its own controller and can be told to refresh itself in a low-power mode, which acts more like SRAM).




Yet there are various designs that are both easily accessible ''and'' keep their state.
Yet there are various designs that are both easily accessible ''and'' keep their state.


It's actually a gliding scale of various properties.  
And there is a gliding scale of various properties in that area as well.
We may well call it NVM (non-volatile memory), when grouping a lot of them and don't yet care about further properties - like how often we may read or write or how difficult that is. Say, some variants of EEPROM aren't the easiest to deal with, and consider that Flash, now very common and quite convenient, is a development from EEPROM.
 
We may well call it NVM (non-volatile memory) when we haven't yet gotten to some more specific properties, like how often we may read or write, or how difficult that is.


When we talk about NVRAM rather than NVM when we are often pointing at more specific designs,  
Say, some variants of EEPROM aren't the easiest to deal with. We like Flash a whole lot better, even though it's basically a development from EEPROM. But both wear out.
often where we can fairly easily use it and it happens to stick around,
like in FRAM, MRAM, and PRAM, or nvSRAM or even BBSRAM.


NVRAM on the other hand tends to be easier, more reisable, like FRAM, MRAM, and PRAM, or nvSRAM or even BBSRAM.


FRAM - Ferroelectric RAM, which resembles DRAM but uses a ferroelectric material,
 
: easier to access than Flash
FRAM - Ferroelectric RAM
: seems to have a read limit rather than a write limit?, but that limit is also something like 1E14 and you are ''unlikely'' to use it so intensely to reach that any time soon.
: functions more like flash, also limited with use (but with many more cycles)
: read process is destructive (like e.g DRAM), so you need a write-after-read to keep data around
: so it's great for things like constant logging, which would be terrible for Flash
: so it's great for things like constant logging, which would be terrible for Flash
https://electronics.stackexchange.com/questions/58297/whats-the-catch-with-fram
: https://electronics.stackexchange.com/questions/58297/whats-the-catch-with-fram
 






nvSRAM - SRAM and EEPROM stuck on the same chip.
nvSRAM - SRAM and EEPROM stuck on the same chip.
: seems intended as a practical improvement on BBSRAM
: and/or a "access quickly, occasionally write a chunk to EEPROM" style of data logging, black boxes, that sort of thing
: https://en.wikipedia.org/wiki/NvSRAM
: https://en.wikipedia.org/wiki/NvSRAM


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: feels like cheating, but usefully so.
: feels like cheating, but usefully so.


-->




Revision as of 22:38, 5 September 2023

The lower-level parts of computers

General: Computer power consumption · Computer noises

Memory: Some understanding of memory hardware · CPU cache · Flash memory · Virtual memory · Memory mapped IO and files · RAM disk · Memory limits on 32-bit and 64-bit machines

Related: Network wiring notes - Power over Ethernet · 19" rack sizes

Unsorted: GPU, GPGPU, OpenCL, CUDA notes · Computer booting



"What Every Programmer Should Know About Memory" is a good overview of memory architectures, RAM types, reasons bandwidth and access speeds vary.


RAM types

✎ This article/section is a stub — some half-sorted notes, not necessarily checked, not necessarily correct. Feel free to ignore, or tell me about it.


DRAM - Dynamic RAM

lower component count per cell than most (transistor+capacitor mainly), so high-density and cheaper
yet capacitor leakage means this has to be refreshed regularly, meaning a DRAM controller, more complexity and higher latency than some
(...which can be alleviated and is less of an issue when you have multiple chips)
this or a variant is typical as main RAM, due to low cost per bit


SDRAM - Synchronous DRAM - is mostly a practical design consideration

...that of coordinating the DRAM via an external clock signal (previous DRAM was asynchronous, manipulating state as soon as lines changed)
This allows the interface to that RAM to be a predictable state machine, which allows easier buffering, and easier interleaving of internal banks
...and thereby higher data rates (though not necessarily lower latency)
SDR/DDR:
DDR doubled busrate by widening the (minimum) units they read/write (double that of SDR), which they can do from single DRAM bank(verify)
similarly, DDR2 is 4x larger units than SDR and DDR3 is 8x larger units than SDR
DDR4 uses the same width as DDR3, instead doubling the busrate by interleaving from banks
unrelated to latency, it's just that the bus frequency also increased over time.


Graphics RAM refers to varied specialized

Earlier versions would e.g. allow reads and writes (almost) in parallel, making for lower-latency framebuffers
"GDDR" is a somewhat specialized form of DDR SDRAM



SRAM - Static RAM

Has a higher component count per cell (6 transistors) than e.g. DRAM
Retains state as long as power is applied to the chip, no need for refresh, also making it a little lower-latency
no external controller, so simpler to use
e.g used in caches, due to speed, and acceptable cost for lower amounts


PSRAM - PseudoStatic RAM

A tradeoff somewhere between SRAM and DRAM
in that it's DRAM with built-in refresh, so functionally it's as standalone as SRAM and slower but you can have a bunch more of it for the same price - e.g. SRAM tends to
(yes, DRAM can have built-in refresh, but that's often points a sleep mode that retains state without requiring an active DRAM controller)



On ECC

Buffered/registered RAM

EPROM, EEPROM, and variants

PROM is Programmable ROM

can be written exactly once

EPROM is Erasable Programmable ROM.

often implies UV-EEPROM, erased with UV shone through a quartz window.

EEPROM's extra E means Electrically Eresable

meaning it's now a command.
early EEPROM read, wrote, and erased (verify) a single byte at a time. Modern EEPROM can work in alrger chunks.
you only get a limited amount of erases (much like Flash. Flash is arguably just an evolution of EEPROM)


Flash memory (intro)

✎ This article/section is a stub — some half-sorted notes, not necessarily checked, not necessarily correct. Feel free to ignore, or tell me about it.


PRAM

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